Report: Google is reportedly working with AMD on a new TPU, raising new questions for the AI chip supply chain

Alphabet’s Google is reportedly collaborating with AMD for the design of its next generation Tensor Processing Unit, or TPU, according to a market report published by Yahoo Finance and syndicated by Barchart on Aug. 20. The report frames the change as a move away from the standard partner model that has, in recent TPU cycles, involved Broadcom playing a major role in components and infrastructure around Google’s AI accelerators.

TPUs are Google’s specialized AI chips designed to accelerate machine-learning workloads, particularly the large-scale training and inference used in products like search and cloud AI services. For chip makers, TPU programs matter because they can translate into design wins, manufacturing-related demand, and long-term platform relationships, even when the buying and integration decisions ultimately sit with Google and its data-center partners.

In the report, the “10th-generation” TPU is described as the key element in the story, with AMD expected to be part of the design collaboration rather than simply acting as an outside technology supplier. The idea is less about a one-off component drop-in and more about whether AMD’s architecture and ecosystem can become embedded in the next TPU platform cycle.

That distinction is important for AMD because its revenue exposure is typically linked to how widely its chips and related software tooling are adopted in the compute stacks that power AI systems. If AMD is pulled deeper into a TPU design effort, it could mean more durable influence over performance characteristics, system integration choices, and the mix of CPUs, accelerators, and networking components that surround the TPU in a data-center rack.

The report also arrives at a time when AI chip customers are wrestling with procurement, power efficiency, packaging constraints, and supply continuity. Even small changes in who collaborates on a platform can ripple outward into manufacturing schedules, testing and validation work, and the way partners align around firmware, compilers, and deployment tooling that make the hardware usable at scale.

However, the market report stops short of providing the kind of detail investors typically look for, such as firm timelines, the scope of AMD’s work, expected volumes, or whether the collaboration replaces existing Broadcom-linked relationships entirely. There is also no disclosure in the syndication post of any confirmed contract terms, specific chip models, or quantified financial impact for AMD. Until Google or AMD provides direct confirmation, the claims should be read as “reported” rather than settled.

Still, the possibility of a TPU design collaboration with AMD is consistent with a broader pattern in the AI hardware sector: hyperscalers and AI platforms often diversify their supplier and partner base to reduce single points of failure and to speed innovation cycles. If AMD can demonstrate that it contributes to higher throughput, lower cost per inference, or better system-level efficiency for the TPU platform, it could strengthen its position in a market that increasingly evaluates vendors on performance-per-watt and deployability as much as raw benchmarks.

What to watch next is confirmation, either from Google, AMD, or both, about the TPU generation referenced in the report and the practical scope of AMD’s involvement. Also important will be any follow-on statements about expected delivery timing, integration requirements, and whether AMD participation affects the procurement mix for the surrounding components that make the TPU system work in real deployments.